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Portrait of Naga Nanda Sai Palanki smiling, wearing a black suit and white shirt with his arms folded

Naga Nanda Sai Palanki · “Nandu”

Currently @ Microchip Technology, Austin TX

I break chips on purpose — then figure out why.

Hardware Validation Engineer3+ years in hardware validationAustin, TX

Open to Hardware Validation, Post-Silicon Validation, and Platform Validation roles in the USA.

LinkedIn [email protected]

Experience

Microchip Technology

Jul 2025 – PresentHardware Validation Engineer, Austin, TX
  • Performed post-silicon board bring-up on evaluation platforms, including power sequencing, clock validation and debug connectivity checks.
  • Validated PCIe Gen4 link behavior, including link training, LTSSM state transitions and ASPM power states, across endpoint device types including storage controllers and connectivity chips.
  • Executed functional and regression testing on I2C, SPI, UART and GPIO interfaces, including fault and error-injection scenarios.
  • Used oscilloscopes, logic analyzers, protocol analyzers and DMMs to investigate and debug interface and signal-level failures.
  • Developed Python and Bash automation on Linux to run tests, control lab instruments via VISA, collect diagnostics and compare results across silicon revisions.
  • Reproduced and root-caused test failures, capturing waveforms and register-state data with firmware and design teams to drive hardware bug resolution.
  • Supported EVT, DVT and PVT qualification using thermal chambers and voltage margin tools, validating hardware stability across full temperature and voltage operating ranges for production sign-off.

STMicroelectronics

Aug 2021 – Jun 2023Hardware Validation Engineer, Bangalore, India
  • Validated I2C, SPI and UART/USART peripheral interfaces across multiple operating modes and configurations.
  • Tested UART in polling, interrupt and DMA transfer modes across varying baud rates, verifying framing, parity and overrun error recovery.
  • Supported board bring-up, including power rail checks, oscillator and PLL behavior, clock distribution and SWD/JTAG debug connectivity.
  • Captured and analyzed I2C, SPI and UART waveforms, comparing register states to isolate firmware, configuration, board or silicon-level issues.
  • Developed Python, Bash and Embedded C scripts on Linux to automate validation and regression testing, and analyzed failure logs for recurring defect patterns across successive silicon tape-outs.

Projects

  • Interactive

    BenchOS

    A working desktop inside the browser, with draggable windows, a terminal and a chip map of my work.

    Launch BenchOS ↗
  • Interactive

    UART Scope

    A live decoder that draws the waveform for your text, then catches injected parity and framing faults.

    Try the scope →
  • B.Tech final year project

    FPGA multiplier

    A high-speed, low-area multiplier design implemented on a Spartan 3E FPGA.

    Read the summary →
  • Interactive

    Chip Map

    My validation work laid out like a silicon die, with a block for each area.

    Explore the map →

At work

  • Microchip Technology

    PCIe Gen4 link validation

    Link training, LTSSM state transitions and ASPM power states across storage controllers and connectivity chips.

  • Microchip Technology

    Lab automation

    Python and Bash scripts that run tests, control instruments over VISA and compare results across silicon revisions.

  • Microchip Technology

    Production qualification

    EVT, DVT and PVT testing with thermal chambers and voltage margin tools across full operating ranges.

  • STMicroelectronics

    UART validation across modes

    Polling, interrupt and DMA modes across baud rates, verifying framing, parity and overrun error recovery.

Skills

PCIe Gen4I2CSPIUARTPythonPyVISALinuxOscilloscopesLogic analyzersJTAG/SWDEVT/DVT/PVTJIRA
Protocols
PCIe Gen4 (LTSSM, link training, ASPM power states), NVMe (storage device qualification), I2C, SPI, UART/USART, GPIO
Validation
Board bring-up, power sequencing, clock and PLL validation, functional and regression testing, fault and error injection, PVT margin testing, server platform hardware qualification
Lab equipment
Oscilloscopes, logic analyzers, protocol analyzers, DMMs, thermal chambers, power supplies, ST-Link/SWD and JTAG debuggers
Automation
Python (test automation, instrument control, log parsing), Bash and shell scripting, Embedded C, Linux CLI
Also
Root-cause analysis, defect tracking (JIRA), register-level datasheet compliance verification

Publication

B.Tech Final Year Project Publication — REVISTA GEINTEC, Vol. 11, July 2021

Design of High Speed and Low Area Confined Multiplier on FPGA

Compared a serial multiplier with an advanced multiplier using RTL simulation, replacing single-bit adders with multiplexers to reduce FPGA resources, latency, area and power. Simulated and synthesized in Xilinx ISE 14.7 and implemented on a Spartan 3E FPGA.

Kandagatla Ravi Kumar, Cheeli Priyadarshini, Kanakam Bhavani, Ankam Varun Sundar Kumar and Palanki Naga Nanda Sai. Pages 2736–2746.

Education

M.S. in Computer Science

Aug 2023 – May 2025University of North Texas

B.Tech in Electronics and Communication Engineering

Jun 2017 – May 2021Lakireddy Bali Reddy College of Engineering (LBRCE), India

Resume

Open resume

F-1 OPT STEM — authorized to work in the USA through June 2028

Playground

Launch BenchOSThe full desktop

Link training, LTSSM state transitions and ASPM power states across storage controllers and connectivity chips.

Python and Bash scripts on Linux that execute tests, control instruments over VISA and compare silicon revisions.

Power sequencing and rail checks, clock, oscillator and PLL behavior, and SWD/JTAG debug connectivity.

Polling, interrupt and DMA modes across baud rates, verifying framing, parity and overrun recovery.

Waveforms and register state that isolate firmware, configuration, board or silicon-level issues.

EVT, DVT and PVT testing with thermal chambers and voltage margin tools for production sign-off.